A basic, practical, introductory textbook for professionals and students, this text explains how a designer can be more effective through the use of the Verilog hardware description language to simulate and document a design. By understanding simulation, a designer can simulate a design to see if a design works before it is built. This gives the designer an opportunity to try different ideas. Documentation allows a designer to maintain and reuse a design more easily. Verilog's intrinsic hierarchical modularity enables the designer to easily reuse portions of the design as `intellectual property' or `macro-cells'. Some of the formal Verilog syntax are presented here, along with definitions and practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. However, the book has over 100 examples that are used to illustrate aspects of the language. In the later chapters the focus is on working with modelling style and explaining why and when one would use different elements of the language, and there is a chapter on state machine modelling. There is also a chapter on test benches and testing strategy as well as a chapter on debugging.
- Hardback | 328 pages
- 165.1 x 230 x 25.4mm | 746.98g
- 01 Jul 1997
- Kluwer Academic Publishers
- Boston, MA, United States
- index, tables
Table of contents
1. Introduction. 2. Introduction to the VERILOG Language. 3. Structural Modeling. 4. Behavioral Modeling. 5. Operators. 6. Working with Behavioral Modeling. 7. User-Defined Primitives. 8. Parameterized Modules. 9. State Machines. 10. Modeling Tips. 11. Modeling Style Trade-offs. 12. Test Benches and Test Management. 13. Common Errors. 14. Debugging a Design. Appendix A: Gate Level Details. Appendix B: Example Summary.