VLSI - Compatible Implementations for Artificial Neural Networks

VLSI - Compatible Implementations for Artificial Neural Networks

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This book introduces several state-of-the-art VLSI implementations of artificial neural networks (ANNs). It reviews various hardware approaches to ANN implementations: analog, digital and pulse-coded. The analog approach is emphasized as the main one taken in the later chapters of the book. The area of VLSI implementation of ANNs has been progressing for the last 15 years, but not at the fast pace originally predicted. Several reasons have contributed to the slow progress, with the main one being that VLSI implementation of ANNs is an interdisciplinaly area where only a few researchers, academics and graduate students are willing to venture. The work of Professors Fakhraie and Smith, presented in this book, is a welcome addition to the state-of-the-art and will greatly benefit researchers and students working in this area. Of particular value is the use of experimental results to backup extensive simulations and in-depth modeling. The introduction of a synapse-MOS device is novel. The book applies the concept to a number of applications and guides the reader through more possible applications for future work. I am confident that the book will benefit a potentially wide readership. M. I. Elmasry University of Waterloo Waterloo, Ontario Canada Preface Neural Networks (NNs), generally defined as parallel networks that employ a large number of simple processing elements to perform computation in a distributed fashion, have attracted a lot of attention in the past fifty years. As the result. many new discoveries have been made.
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Product details

  • Hardback | 194 pages
  • 162.56 x 236.22 x 20.32mm | 385.55g
  • Dordrecht, Netherlands
  • English
  • 1997 ed.
  • XXIX, 194 p.
  • 0792398254
  • 9780792398257

Table of contents

List of Figures. Foreword. Preface. 1. Introduction and Motivation. 2. Review of Hardware-Implementation Techniques. 3. Generalized Artificial Neural Networks (GANNs). 4. Foundations: Architecture Design. 5. Design, Modeling, and Implementation of a Synapse-MOS Device. 6. Synapse-MOS Artificial Neural Networks (SANNs) 7. Analog Quadratic Neural Networks (AQNNs) 8. Conclusion and Recommendations for Future Work. Appendix A: Review of Nonvolatile Semiconductor Memory Devices. Appendix B: Scaling Effects. Appendix C: Performance Evaluation. References. Index.
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