VHDL Coding Styles and Methodologies
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VHDL Coding Styles and Methodologies

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VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.
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Product details

  • Mixed media product | 455 pages
  • 172.72 x 256.54 x 30.48mm | 1,179.33g
  • Dordrecht, Netherlands
  • English
  • Revised
  • 2nd ed. 1999
  • XIX, 455 p. With online files/update.
  • 0792384741
  • 9780792384748

Table of contents

Preface. 1.0. VHDL Overview and Concepts. 2.0. Basic Language Elements. 3.0. Control Structures. 4.0. Drivers. 5.0. VHDL Timing. 6.0. Elements of Entity/Architecture. 7.0. Subprograms. 8.0. Packages. 9.0. User Defined Attributes, Specifications, and Configurations. 10.0. Design for Synthesis. 11.0. Functional Models and Testbenches. 12.0. UART Project. Appendix A: VHDL 93 and VHDL 87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package Textio. Appendix D: STD_Logic_Textio. Appendix E: Package STD_Logic_1164. Appendix F: Numeric_STD. Appendix G: STD_Logic_Unsigned. Appendix H: STD_Logic_Signed. Appendix I: STD_Logic_Arith. Appendix J: STD_Logic_Misc. Appendix K: VHDL Predefined Attributes. Index.
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