VHDL Answers to Frequently Asked Questions
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VHDL Answers to Frequently Asked Questions

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Description

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. TItis book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages of common utilities that are useful in the generation of debug code and testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.
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Product details

  • Hardback | 384 pages
  • 186.2 x 262.1 x 33.3mm | 1,094.82g
  • Dordrecht, Netherlands
  • English
  • Revised
  • 2nd ed. 1998
  • XXIX, 384 p.
  • 0792381157
  • 9780792381150
  • 2,332,856

Table of contents

Preface. About the Disk. Notation Conventions: Symbols. Syntactic Description. 1. Language Elements. 2. Arrays. 3. Drivers. 4. Subprograms. 5. Packages. 6. Models. 7. Synthesis. 8. Design Verification and Testbench. 9. Potpourri. 10. Design for Reuse. Appendices: A. VHDL'93 and VHDL'87 Syntax Summary. B. Package STANDARD. C. Package TEXTIO. D. Package STD_LOGIC_1164. E. Package STD_LOGIC_ARITH. F. VHDL Predefined Attributes. Bibliography. Index.
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