System on Chip Interfaces for Low Power Design

System on Chip Interfaces for Low Power Design

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System on Chip Interfaces for Low Power Design provides a top-down understanding of interfaces available to SoC developers, not only the underlying protocols and architecture of each, but also how they interact and the tradeoffs involved. The book offers a common context to help understand the variety of available interfaces and make sense of technology from different vendors aligned with multiple standards. With particular emphasis on power as a factor, the authors explain how each interface performs in various usage scenarios and discuss their advantages and disadvantages. Readers learn to make educated decisions on what interfaces to use when designing systems and gain insight for innovating new/custom interfaces for a subsystem and their potential impact.
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Product details

  • Paperback | 406 pages
  • 191 x 235 x 22.86mm | 820g
  • Morgan Kaufmann Publishers In
  • San Francisco, United States
  • English
  • 0128016302
  • 9780128016305

Table of contents

SoC Design Fundamentals and Evolution
Understanding Power Consumption Fundamentals
Generic SoC Architecture and Components
Display Interfaces
Multimedia Interfaces
Communication Interfaces
Memory Interfaces
Security Interfaces
Power Interfaces
Sensor Interfaces
Input Device Interfaces
Debug Interfaces

Appendix A: USB3.0 Appendix B: Industry Consortiums Appendix C: Overview of Intel SoC: Baytrail
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About Sanjeeb Mishra

Sanjeeb Mishra is a Validation Architect with Intel. He has 15 years of experience ranging from hardware system design to SOC validation for telecom, consumer electronics, PC and mobility products; and has specific expertise on SoC architecture for mobile devices. Neeraj Kumar Singh is a Platform Architect for tablet platforms at Intel. Prior to this he worked on CPU, Graphics and Chipset validation tools. His areas of expertise are hardware software co-design, SoC system architecture, and system software design and development. Vijayakrishnan Rousseau is a Technical Lead at Intel. He has 15 years of experience in GPU and SOC validation with specialization in Display interfaces like HDMI, Display Port and Emulation.
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