Synchronous Precharge Logic
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Synchronous Precharge Logic

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Description

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.
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Product details

  • Paperback | 112 pages
  • 149.86 x 228.6 x 7.62mm | 181.44g
  • United States
  • English
  • 0123985277
  • 9780123985279

Table of contents

Precharge Logic Basics
Timing
Transistor Sizing
Noise Tolerance
Topology Considerations
Other Precharge Logic Styles
Clocked Set-Reset Latches
Layout Considerations
Appendix: Logical Effort
References
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About Marek Smoszna

Marek Smoszna is a memory design engineer at NVIDIA Corporation. He was born in Poland in 1972. He received his BS and MS in electrical engineering from Rensselaer Polytechnic Institute in 1995 and 1996, respectively. He holds two patents in the area of memory design with several other patent applications filed. His interests include high speed circuit and memory design. When not doing circuit design he can be found with his children at the beach.
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