VHDL Design Representation and Synthesis

VHDL Design Representation and Synthesis

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For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.show more

Product details

  • Paperback | 651 pages
  • 180.34 x 231.14 x 40.64mm | 1,020.58g
  • Pearson Education (US)
  • Prentice Hall
  • Upper Saddle River, United States
  • English
  • 2nd edition
  • 0130216704
  • 9780130216700

Back cover copy

"VHDL Design Representation and Synthesis, Second Edition" is an exceptionally clear, thorough, and up-to-date introduction to today's leading approach to hardware design: synthesis using a hardware description language and today's leading synthesis tools. Armstrong and Gray begin with an introduction to structured design, and a unified explanation of the VHDL language and its key constructs. Next, they introduce the modeling process step by step, using many examples at varying levels of abstraction, and demonstrate techniques designed to maximize both simulation efficiency and compatibility with synthesis tools. Design tools: editors, simulators, checkers, analyzers, optimizers, and synthesizers VHDL: major constructs, lexical description, source files, data types, data objects, statements, and advanced features Fundamental VHDL modeling techniques: propagation and time delay, concurrency, scheduling, combinational logic, sequential logic, and primitives Integrating VHDL into the design flow, from executable specifications at the algorithmic level through implementations at the gate or cell level Modling PLDs, gate arrays, FPGAs (using Xilinx tools) and standard cells (using Synopsys tools) This edition contains extensive new coverage of multilevel modeling, design with standard parts and ASICs data and control unit design, modeling for synthesis, and more. Review problems are included in each chapter, and over 300 references are provided. If you intend to design with VHDL, this is the book to start with.show more

About James R. Armstrong

DR. JAMES R. ARMSTRONG and DR. F. GAIL GRAY are Professors of Electrical and Computer Engineering at Virginia Tech. Dr. Armstrong teaches graduate and undergraduate courses in computer architecture, HDLs, and logic design. He was a member of the original IEEE standardization committee; authored Chip Level Modeling With VHDL, and co-authored Structured Logic Design With VHDL, both from Prentice Hall. Dr. Gray teaches graduate and undergraduate courses in computer engineering, logic design, hardware description languages, coding theory, fault tolerant computing, testing, and microprocessor system design. His work has been published by IEEE Transactions on Computers; Journal of VLSI Signal Processing for Signal, Image, and Video Technology; Design Automation Conference; the VHDL International Users Forum; and many other leading journals and conferences.show more

Table of contents

Preface. 1. Structured Design Concepts. The Abstraction Hierarchy. Textual vs Pictorial Representations. Types of Behavioral Descriptions. Design Process. Structural Design Decomposition. The Digital Design Space.2. Design Tools. CAD Tool Taxonomy. Schematic Editors. Simulators. The Simulation System. Simulation Aids. Applications of Simulation. Synthesis Tools.3. Basic Features of VHDL. Major Language Constructs.3. Lexical Description. Character Set. VHDL Source File. Data Types. Data Objects. Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL 93. Summary.4. Basic VHDL Modeling Techniques. Modeling Delay in VHDL. The VHDL Scheduling Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives.5. Algorithmic Level Design. General Algorithmic Model Development in the Behavioral Domain. Representation of System Interconnections. Algorithmic Modeling of Systems.6. Register Level Design. Transition from Algorithmic to Data Flow Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine.7. Gate Level and ASIC Library Modeling. Accurate Gate Level Modeling. Error Checking. Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate Level Models. Modeling Races and Hazards. Approaches to Delay Control.8. HDL-Based Design Techniques. Design of Combinational Logic Circuits. Design of Sequential Logic Circuits. Design of Microprogrammed Control Units.9. ASICs and the ASIC Design Process. What is an ASIC? ASIC Circuit Technology. Types of ASICs. The ASIC Design Process. FPGA Synthesis.10. Modeling for Synthesis. Behavioral Model Development. The Semantics of Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits. Shared Resources. Flattening and Structuring. Effect of Modeling Style On Circuit Complexity.11. Integration of VHDL into a Top-Down Design Methodology. Top-Down Design Methodology. Sobel Edge Detection Algorithm. System Requirements Level. System Definition Level. Architecture Design. Detailed Design at the RTL Level. Detailed Design at the Gate Level.12. Synthesis Algorithms for Design Automation. Benefits of Algorithmic Synthesis. Algorithmic Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art in High-Level Synthesis. Automated Synthesis of VHDL Constructs.Index. References. About the Authors. Index.show more

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