Sequential Logic Testing and Verification

Sequential Logic Testing and Verification

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In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care- fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte- gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.
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Product details

  • Hardback | 214 pages
  • 163.1 x 243.3 x 19.8mm | 547.41g
  • Dordrecht, Netherlands
  • English
  • 1992 ed.
  • XIX, 214 p.
  • 0792391888
  • 9780792391883

Table of contents

List of Figures.- List of Tables.- Preface.- Acknowledgements.- 1 Introduction.- 1.1 IC Design Systems.- 1.2 Implementation Verification.- 1.3 Testing.- 1.4 Synthesis For Testability.- 1.5 Outline.- 2 Sequential Test Generation.- 2.1 Preliminaries.- 2.2 Methods for Sequential Test Generation.- 2.2.1 Random Techniques.- 2.2.2 Deterministic Techniques.- 2.3 Test Generation Strategy.- 2.4 Cover Extraction and Combinational ATG.- 2.5 Justification.- 2.6 Initialization of Circuits.- 2.7 State Differentiation.- 2.8 Identification of Redundant Faults.- 2.9 Test Generation Results Using STEED.- 2.10 Conclusions.- 3 Test Generation Using RTL Descriptions.- 3.1 Preliminaries.- 3.2 Previous Work.- 3.3 Global Strategy for Test Generation.- 3.4 State Justification.- 3.5 Indexed Backtracking.- 3.6 Conflict Resolution.- 3.6.1 Assembling the equations.- 3.7 State Differentiation.- 3.8 Test Generation Results Using ELEKTRA.- 3.9 Conclusions.- 4 Sequential Synthesis for Testability.- 4.1 Preliminaries.- 4.1.1 Eliminating Sequential Redundancies.- 4.2 Previous Work.- 4.3 Theoretical Results.- 4.3.1 An Unconditional Testability Theorem.- 4.3.2 Logic Partitioning.- 4.4 The Synthesis and Test Strategy.- 4.5 Detection of Invalid States.- 4.6 Detection of Equivalent States.- 4.7 Experimental Results.- 4.8 Conclusions.- 5 Verification of Sequential Circuits.- 5.1 Preliminaries.- 5.2 Previous Work.- 5.3 Implicit STG Traversal.- 5.3.1 Incompletely-specified machines.- 5.4 Implicit STG Enumeration.- 5.4.1 Traversal versus enumeration.- 5.5 Experimental Results.- 5.6 Conclusions.- 6 Symbolic FSM Traversal Methods.- 6.1 Preliminaries.- 6.1.1 Binary Decision Diagrams.- 6.1.2 Sets and Characteristic Functions.- 6.2 Traversal by Recursive Range Computation.- 6.3 Traversal based on Transition Relations.- 6.3.1 Iterative Squaring.- 6.3.2 Detecting Equivalent States.- 6.4 Depth-First Geometric Chaining.- 6.4.1 An Autonomous Counter.- 6.4.2 A Loop Counter.- 6.5 A Mixed Traversal Algorithm.- 6.5.1 Introduction.- 6.5.2 k-Convergence and t-Periodicity.- 6.5.3 Traversing Cascaded Machines.- 6.5.4 Traversing Mutually Interacting Machines.- 6.5.5 Generalization to Multiple Submachines.- 6.5.6 Input-Selection-Based Traversal.- 6.6 Implementation of Algorithm.- 6.7 Experimental Results.- 6.8 Conclusions.- 7 Conclusions.- 7.1 Test Generation.- 7.2 Synthesis for Testability.- 7.3 Verification.- 7.4 Directions for Future Work.
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