Power Trade-offs and Low-Power in Analog CMOS ICs

Power Trade-offs and Low-Power in Analog CMOS ICs

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Description

This volume concerns power, noise and accuracy in CMOS Analog IC Design. The authors show that power, noise and accuracy should be treated in a unitary way, as the three are inter-related. The book discusses all possible practical power-related specs at circuit and architecture level.
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Product details

  • Paperback | 214 pages
  • 155 x 235 x 15.24mm | 373g
  • New York, NY, United States
  • English
  • Softcover reprint of the original 1st ed. 2002
  • XX, 214 p.
  • 1441949437
  • 9781441949431

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Table of contents

Selected Symbols and Abbreviations. 1: Introduction. 1.1. Motivation. 1.2. Problem definition. 1.3. Scope and outline. References. 2: Power considerations in sub-micron digital CMOS. 2.1. Introduction. 2.2. Fundamental limits. 2.3. From fundamental limits to practical limits of power. An architecture level approach. 2.4. S/N ratio and power in fixed point applications. 2.5. Adders and computational power. 2.6. Ways to low-power in digital. 2.7. Example of a digital video filter. 2.8. Conclusions. References. 3: Power considerations in sub-micron analog CMOS. 3.1. Introduction. 3.2. Process tuning towards digital needs. Consequences on analog. 3.3. Fundamental limits. 3.4. From fundamental limits to practical limits of power. Noise related power. 3.5. From fundamental limits to practical limits of power. Mismatch related power. 3.6. Power estimations in continuous time filters. 3.7. Conclusion. References. 4: Gm-C integrators for low-power and low voltage applications. A gaussian polyphase filter for mobile transceivers in 0.35mum CMOS. 4.1. Introduction. 4.2. Large swing and high linearity transconductor. 4.3. Low voltage current Gm-C integrator with high power efficiency. 4.4. Low-power luminance video filter. Noise driven power. 4.5. Low-power, gaussian, polyphase filter for mobile transceivers. Matching driven power. 4.6. Conclusions.References. 5: Chopping: a technique for noise and offset reduction. 5.1. Introduction. 5.2. Ways to reduce offsetand 1/f noise. 5.3. Chopping seen as a modulation technique. 5.4. Noise modulation. 5.5. Chopped amplifiers and offset reduction. 5.6. Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. Chopping at high frequency. 5.7. A low-power bandgap voltage reference. 5.8. Conclusions. References. 6: Low-noise, low residual offset, chopped amplifiers for high-end applications. 6.1. Introduction. 6.2. Low-pass filtering in a digital audio system. Application specific constraints. 6.3. The gain stage. 6.4. A low noise, low residual offset, chopped amplifier in 0.8mm CMOS. 6.5. A low noise, low residual offset, chopped amplifier in 0.5mm CMOS. 6.6. Conclusions. References. 7: A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter. 7.1. Introduction. 7.2. Bitstream D/A conversion system with time-discrete filtering. 7.3. S-D modulators and noise shaping. 7.4. Semidigital FIR filter principles. 7.5. Semidigital FIR filter design. 7.6. Noise properties of the D/A interface. 7.7. Realisation. 7.8. Experimental results. 7.9. Interpolative D/A converter with Sinc approximation in the time domain. 7.10. Conclusions. References. 8: Conclusions. 8.1. Summary. 8.2. Conclusions. 8.3. Original contributions. 8.4. Recommendations for further research. Appendix 1. Appendix 2. Appendix 3. Dankwoord. Curriculum Vitae & List of Publications.
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