Parallel Processing on VLSI Arrays

Parallel Processing on VLSI Arrays

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Guest Editor: JOSEF A. NOSSEK This is a special issue of the Journal of VLSI Signal Processing comprising eight contributions invited for publica- tion on the basis of novel work presented in a special session on "Parallel Processing on VLSI Arrays" at the International Symposium on Circuits and Systems (ISCAS) held in New Orleans in May 1990. Massive parallelism to cope with high-speed requirements stemming from real-time applications and the restrictions in architectural and circuit design, such as regularity and local connectedness, brought about by the VLSI technology are the key questions addressed in these eight papers. They can be grouped into three subsections elaborating on: * Simulation of continuous physical systems, i. e. , numerically solving partial differential equations. * Neural architectures for image processing and pattern recognition. * Systolic architectures for implementing regular and irregular algorithms in VLSI technology. The paper by A. Fettweis and O. Nitsche advocates a signal processing approach for the numerical integration of partial differential equations (PD Es). It is based on the principles of multidimensional wave digital filters (MDWDFs) thereby preserving the passivity of energy dissipating physical systems. It is particularly suited for systems ofPDEs involving time and finite propagation speed. The basic ideas are explained using Maxwell's equa- tions as a vehicle for the derivation of a multidimensional equivalent circuit representing the spatially infinitely extended arrangement with only very few circuit elements.
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Product details

  • Hardback | 140 pages
  • 210 x 279 x 9.65mm | 595g
  • Dordrecht, Netherlands
  • English
  • Reprinted from JOURNAL OF VLSI SIGNAL PROCESSING, 3: 1/2, 1991
  • 140 p.
  • 0792392000
  • 9780792392002

Table of contents

Numerical Integration of Partial Differential Equations Using Principles of Multidimensional Wave Digital Filters.- Signal Processing Using Cellular Neural Networks.- Nonlinear Analog Networks for Image Smoothing and Segmentation.- A Systolic Array for Nonlinear Adaptive Filtering and Pattern Recognition.- Control Generation in the Design of Processor Arrays.- A Sorter-Based Architecture for a Parallel Implementation of Communication Intensive Algorithms.- Feedforward Architectures for Parallel Viterbi Decoding.- Carry-Save Architectures for High-Speed Digital Signal Processing.
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