Parallel Computer Organization and Design
Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software.
- Online resource
- 05 Nov 2012
- Cambridge University Press (Virtual Publishing)
- Cambridge, United Kingdom
- 206 b/w illus. 49 tables 95 exercises
'... an excellent tutorial of computer architecture fundamentals from the basic technology via processor and memory architecture to chip multiprocessors ... an excellent instructive book worth using.' Uri Weiser, Technion '... an excellent textbook which can serve both as an introduction to multi-core and parallel architectures, as well as a reference for engineers and researchers.' Olivier Temam, INRIA, France '... fills an urgent need for a comprehensive and authoritative yet approachable tutorial and reference text for advanced computer architecture topics. All of the key principles and concepts covered in Wisconsin's three-course computer architecture sequence are addressed in a well-organized, thoughtful, and pedagogically appealing manner, without overwhelming the reader with distracting trivia or an excess of quantitative data ... the final chapter on quantitative evaluation - a true gem! - is a unique and valuable asset that will clearly set this book apart from its competition.' Mikko Lipasti, University of Wisconsin, Madison 'Its content is rich, coherent and clear. Its questions are crafted to stimulate creative thinking. I recommend the book as a must read to all graduate students and young researchers and engineers designing computers.' Lixin Zhang, Institute of Computing Technology, Chinese Academy of Sciences 'This is a perfect text for a one semester graduate course.' Lawrence Rauchwerger, Texas A&M University 'It is the best of today's books on the subject, and I plan to use it in my class. It is an up-to-date picture of parallel computing that is written in a style that is clear and accessible.' Trevor Mudge, University of Michigan 'I want to particularly stress the uniquely clear way in which the authors explain the hardest among these topics: coherence, synchronization, and memory consistency.' Manolis Katevenis, University of Crete and Head of the Computer Architecture and VLSI Systems Laboratory, FORTH-ICS 'An excellent book in an area that has long cried out for tutorial material - it will be an indispensable resource to students and educators in parallel computer architecture.' Josep Torrellas, University of Illinois
Table of contents
1. Introduction; 2. Impact of technology; 3. Processor microarchitecture; 4. Memory hierarchies; 5. Multiprocessor systems; 6. Interconnection networks; 7. Coherence, synchronization, and memory consistency; 8. Chip multiprocessors; 9. Quantitative evaluations.
About Michel Dubois
Michel Dubois is a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California (USC) and part of the Computer Engineering Directorate. Before joining USC in 1984, he was a research engineer at the Central Research Laboratory of Thomson-CSF in Orsay, France. He has published more than 150 technical papers on computer architecture and edited two books. He is a Fellow of the IEEE and of the ACM. Murali Annavaram is an Assistant Professor and Robert G. and Mary G. Lane Early Career Chair in the Ming Hsieh Department of Electrical Engineering at the University of Southern California, and part of the Computer Engineering Directorate, where he has developed and taught advanced computer architecture courses. Prior to USC, he spent six years at Intel researching various aspects of future CMP designs. Per Stenstrom is a Professor of Computer Engineering at Chalmers University of Technology, Sweden. He has published two textbooks and over 100 technical papers. He has been a visiting scientist at Carnegie-Mellon University, Stanford University and the University of Southern California, and also was engaged in research at Sun Microsystems on its chip-multithreading technology. He is a Fellow of the IEEE and of the ACM and is a member of the Royal Swedish Academy of Engineering Sciences and the Academia Europaea.