On Optimal Interconnections for VLSI

On Optimal Interconnections for VLSI

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On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts.
Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.
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Product details

  • Hardback | 286 pages
  • 154.94 x 236.22 x 25.4mm | 566.99g
  • Dordrecht, Netherlands
  • English
  • 1995 ed.
  • XVIII, 286 p.
  • 0792394836
  • 9780792394839

Table of contents

List of Figures. List of Tables. 1: Preliminaries. 1.1. Preface. 1.2. The Domain of Discourse: Routing in VLSI Physical Design. 1.3. Overview of the Book. 1.4. Acknowledgements. 2: Area. 2.1. Introduction. 2.2. Performance Bounds for MST-Based Strategies. 2.3. Iterated 1-Steiner (I1S). 2.4. Enhancing I1S Performance. 2.5. Practical Implementation Options for I1S. 2.6. On the Maximum MST Degree. 2.7. Steiner Trees in Graphs. 3: Delay. 3.1. Preliminaries. 3.2. Geometric Approaches to Delay Minimization. 3.3. Minimization of Actual Delay. 3.4. New Directions. 4: Skew. 4.1. Preliminaries. 4.2. An Early Matching-Based Approach. 4.3. DME: Exact Zero Skew with Minimum Wirelength. 4.4. Planar-Embeddable Trees. 4.5. Remarks. 5: Multiple Objectives. 5.1. Minimum Density Trees. 5.2. Multi-Weighted Graphs. 5.3. Prescribed-Width Routing. A: Appendix: Signal Delay Estimators. A.1. Basics. A.2. Accuracy and Fidelity. References. Author Index. Term Index.
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