On-Chip Inductance in High Speed Integrated Circuits

On-Chip Inductance in High Speed Integrated Circuits

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The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies.
On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively.
On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance.
On-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.
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Product details

  • Hardback | 303 pages
  • 161.5 x 243.3 x 23.9mm | 589.68g
  • Dordrecht, Netherlands
  • English
  • 2001 ed.
  • XXII, 303 p.
  • 079237293X
  • 9780792372936

Table of contents

List of Figures. List of Tables. Preface. 1. Introduction. 2. Basic Transmission Line Theory. 3. Evaluating the Transient Response of Linear Networks. 4. Mosfet Current-Voltage Characteristics. 5. Figures of Merit to Characterize the Importance of on-Chip Inductance in Single Lines. 6. Effects of Inductance on the Propagation Delay and Repeater Insertion Process in RLC Lines. 7. Equivalent Elmore Delay for RLC Trees. 8. Characterizing Inductance Effects in RLC Trees. 9. Repeater Insertion in Tree Structured Inductive Interconnect. 10. Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. 11. Exploiting On-Chip Inductance in High Speed Clock Distribution Networks. 12. Accurate and Efficient Evaluation of the Transient Response in RLC Circuits: The DTT Method. 13. On the Extraction of On-Chip Inductance. 14. Conclusions. Bibliography. Appendices. Index. About the Authors.
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