Multithreaded Computer Architecture: A Summary of the State of the ART

Multithreaded Computer Architecture: A Summary of the State of the ART

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Multithreaded computer architecture has emerged as one of the most promising and exciting avenues for the exploitation of parallelism. This new field represents the confluence of several independent research directions which have united over a common set of issues and techniques. Multithreading draws on recent advances in dataflow, RISC, compiling for fine-grained parallel execution, and dynamic resource management. It offers the hope of dramatic performance increases through parallel execution for a broad spectrum of significant applications based on extensions to `traditional' approaches.
Multithreaded Computer Architecture is divided into four parts, reflecting four major perspectives on the topic. Part I provides the reader with basic background information, definitions, and surveys of work which have in one way or another been pivotal in defining and shaping multithreading as an architectural discipline. Part II examines key elements of multithreading, highlighting the fundamental nature of latency and synchronization. This section presents clever techniques for hiding latency and supporting large synchronization name spaces. Part III looks at three major multithreaded systems, considering issues of machine organization and compilation strategy. Part IV concludes the volume with an analysis of multithreaded architectures, showcasing methodologies and actual measurements.
Multithreaded Computer Architecture: A Summary of the State of the Art is an excellent reference source and may be used as a text for advanced courses on the subject.
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Product details

  • Hardback | 400 pages
  • 156 x 233.9 x 25.4mm | 762.05g
  • Dordrecht, Netherlands
  • English
  • 1994 ed.
  • XVI, 400 p.
  • 0792394771
  • 9780792394778

Table of contents

Preface. Part I: Background and Issues. 1. Multithreaded Architectures: Principles, Projects, and Issues; J.B. Dennis, Guang R. Gao. 2. Architectural and Implementation Issues for Multithreading (Panel Discussion); R.A. Iannucci. 3. Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement); W.J. Dally. 4. Programming, Compilation, and Resource-Management Issues for Multithreading (Panel Discussion); R.H. Halstead, Jr. 5. Programming, Compilation, and Resource-Management Issues for Multithreading (Position Statement); R.S. Nikhil. 6. Multithreading: Fundamental Limits, Potential Gains, and Alternatives; D.E. Culler. Part II: Key Elements 7. Low-Cost Support for Fine-Grain Synchronization in Multiprocessors; D. Kranz, Beng-Hong Lim, A. Agarwal, D. Yeung. 8. Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors; J. Laudon, A. Gupta, M. Horowitz. 9. Named State and Efficient Context Switching; P.R. Nuth, W.J. Dally. 10. Ideas for the Design of Multithreaded Pipelines; A.R. Omondi. Part III: Systems. 11. Integrated Support for Heterogeneous Parallelism; G. Alverson, R. Alberson, D. Callahan, B. Koblenz, A. Porterfield, B. Smith. 12. An Architecture for Generalized Synchronization and Fast Switching; K. Ekanadham, S. Gregor, K. Hiraki, R.A. Iannucci, R. Rajkumar. 13. Concurrent Execution of Heterogeneous Threads in the Super-Actor Machine; H.H.J. Hum, Guang R. Gao. Part IV: Analysis. 14. Analysis of Multithreaded Microprocessors under Multiprogramming; D.E. Culler, M. Gunter, J.C. Lee. 15. Exploiting Locality in Hybrid Dataflow Programs; W.A. Najjar, A.P.W. Boehm, W.M. Miller. Index.
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