Low Power Design for Microprocessors and System on Chip

Low Power Design for Microprocessors and System on Chip : Nanometer and System-Level Design

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In highly mobile, frequently wireless applications like cell phones, the trend is towards smaller and lighter weight packaging yet with increasing functionality and lower price. The demand from end users for increased battery service life is considerable. Reducing on-chip power consumption has become a critical challenge for System-on-Chip (SOC) designers. A new way of thinking about Low power will be necessary to succeed in the consumer electronics arena going forward. Low power design techniques will be used from the earliest phase of the design cycle to have the maximum impact on power convergence and optimization.

As Lead Engineers for Intel and Marvell, respectively, Subhomoy Chattopadhyay and Rakesh Patel work daily at the leading edge of R&D on low power design. This book contains an industry perspective on low power design not currently available, with its focus on the deep sub-micron designs currently needed to achieve the functionality/low-power needs described above.
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Product details

  • Hardback | 400 pages
  • 191 x 235mm
  • Morgan Kaufmann Publishers In
  • San Francisco, United States
  • English
  • 0123741491
  • 9780123741493

Table of contents

Introduction to the Importance of Low Power Design; Architectural Optimization for Level Low Power System Design; Platform power estimation and Optimization; Low Power Logic Design Techniques; MOS Device Design and Implications on Low Power Design; Low Power Memory/SRAM Architecture and Design; Average power/Leakage Power Reduction Techniques; Dynamic/Active Power Reduction Techniques; Low Power Estimation techniques (Short Circuit, leakage and Active power); Low Power Estimation and Optimization Tools ? Overview; Power Consideration for Reliability and Power-grid design.
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Review quote

"Other books presently on the market do not address the more difficult practical issues that are encountered by today's state-of-the-art chips."
Don Bouldin, University of Tennessee

"The major strength of the book is the coverazge of all the really crucial aspects of the design of a modern digital system from the power efficiency point of view...It is the first book covering in a systematic way problems and solutions related to ultra deep sub micron design and optimization."
Salvatore Carta, University of Cagliari

"Major strength is a comprehensive "soup to nuts" coverage of low power design and power reduction including architectural tradeoffs and reliability."
Shantanu Ganguly, Qualcom, Inc.
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