Low Power Design in Deep Submicron Electronics

Low Power Design in Deep Submicron Electronics

Edited by  , Edited by 

List price: US$459.00

Currently unavailable

We can notify you when this item is back in stock

Add to wishlist

AbeBooks may have this title (opens in new window).

Try AbeBooks


Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging.
The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems.
Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design.
show more

Product details

  • Hardback | 600 pages
  • 160 x 240 x 35.05mm | 1,013g
  • Dordrecht, Netherlands
  • English
  • 1997 ed.
  • 600 p.
  • 079234569X
  • 9780792345695

Table of contents

Foreword. 1. Introduction; W. Nebel. 2. Application and Technology Forecast; D.J. Frank. 3. Low Power Design Flow and Libraries; M. Laurent, M. Briet. 4. Low Power Circuit and Logic Level Design. 4.1. Modeling; J. Figueras. 4.2. Circuit and Logic Level Design; C. Piguet. 4.3. Power Estimation at the Logic Level; W. Nebel. 4.4. Advanced Power Estimation Techniques; M. Pedram. 5. Power Optimization. 5.1. Layout Optimization; J. Cong, et al. 5.2. Combinational Circuit Optimization; S. Iman, M. Pedram. 5.3. Sequential Synthesis and Optimization for Low Power; E. Macii. 5.4. RT and Algorithmic-Level Optimization for Low Power; E. Macii. 5.5. High Level Synthesis for Low Power; E. Macii. 6. System Level Low Power Design. 6.1. Embedded System Design; S.B. Furber. 6.2. Power Analysis and Design at System Level; K. Roy. 6.3. Software Design for Low Power; K. Roy, M.C. Johnson. 7. Asynchronous Design; S.B. Furber. 8. Low Voltage Technologies; C. Svensson. 9. Case Studies. 9.1. Microprocessor Design; C. Piguet. 9.2. Low Power Applications at System Level; L. Claesen, et al. Index.
show more