Logic Synthesis and Verification

Logic Synthesis and Verification

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Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges.
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
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Product details

  • Hardback | 454 pages
  • 160.5 x 240.8 x 26.9mm | 771.12g
  • Dordrecht, Netherlands
  • English
  • 2002 ed.
  • XV, 454 p.
  • 0792376064
  • 9780792376064

Table of contents

Foreword. Preface. 1: Two-Level Logic Minimization; O. Coudert, T. Sasao. 2: Multi-Level Logic Optimization; M. Fujita, Y. Matsunaga, M. Ciesielski. 3: Flexibility in Logic; E. Sentovich, D. Brand. 4: Multiple-Valued Logic Synthesis and Optimization; E. Dubrovna. 5: Technology Mapping; L. Stok, V. Tiwari. 6: Technology-based Transformations; R. Murgai. 7: Logical and Physical Design: A Flow Perspective; O. Coudert. 8: Logic Synthesis for Low Power; L. Benini, G. de Micheli. 9: Optimization of Synchronous Circuits; S. Hassoun, T. Villa. 10: Asynchronous Control Circuits; L. Lavagno, S.M. Nowick. 11: Ordered Binary Decision Diagrams; R.E. Bryant, C. Meinel. 12: SAT and ATPG: Algorithms for Boolean Decision Problems; W. Kunz, J. Marques-Silva, S. Malik. 13: Combinatorial and Sequential Equivalence Checking; A. Kuehlmann, C.A.J. van Eijk. 14: Static Timing Analysis; Y. Kukimoto, M. Berkelaar, K. Sakallah. 15: The Future of Logic Synthesis and Verification; R.K. Brayton. Appendices: A: About the Authors. B: Author Contact Information. Index.
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