Logic Synthesis Using Synopsys Tm
Logic synthesis has become a fundamental component of the ASIC design flow. The primary focus of this text is Synopsys Design Compiler TM: one of the leading synthesis tools in the EDA marketplace. The book is specially organized to try and assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 "classic scenarios" faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided.
- Hardback | 328 pages
- 157.48 x 238.76 x 25.4mm | 725.74g
- 30 Jun 1995
- Kluwer Academic Publishers
- United States
- references, index
Table of contents
1. High-Level Design Methodology Overview. 2. Coding in HDL for Synthesis. 3. Pre- and Post-Synthesis Simulation. 4. Constraining and Optimizing Designs - I. 5. Constraining and Optimizing Designs - II. 6. Design for Testability.7. Interfacing between CAD Tools. 8. Design Re-Use Using DesignWare. Appendix A. 1. Sample dc-shell scripts. 2. Using Synopsys On-Line Documentation - iview. 3. Synopsys Technology Library. 4. Sample Synopsys Technology Library RAM Model.