Itanium Architecture for Programmers

Itanium Architecture for Programmers : Understanding 64-Bit Processors and EPIC Principles

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This book is centered on Itanium architecture, the new 64-bit Explicitly Parallel Instruction Computing (EPIC) design by Hewlett-Packard and Intel in partnership. Itanium processors reflect a thoroughly new design. They support 64-bit open-source as well as proprietary operating systems and have been selected to replace existing RISC-based server and workstation lines by many of the industry's major system builders. The authors discuss the general principles of computer architecture with working examples. Also included are references, both print and electronic, to guide readers in finding related material. Along with the technical coverage are suggestions about the motivation and rationale for the Itanium architecture, as well as critique and demonstrate how to use its instruction set. Lastly, the book has sample Itanium programs that work with HP-UX assemblers, with GNU and Intel assemblers for Linux, and with the free Ski simulator from HP.show more

Product details

  • Paperback | 576 pages
  • 172.72 x 228.6 x 35.56mm | 861.82g
  • Pearson Education (US)
  • Prentice Hall
  • Upper Saddle River, United States
  • English
  • 0131013726
  • 9780131013728
  • 2,009,532

Back cover copy

Step-by-step guide to assembly language for the 64-bit Itanium processors, with extensive examplesDetails of Explicitly Parallel Instruction Computing (EPIC): Instruction set, addressing, register stack engine, predication, I/O, procedure calls, floating-point operations, and moreLearn how to comprehend and optimize open source, Intel, and HP-UX compiler output Understand the full power of 64-bit Itanium EPIC processors Itanium(R) Architecture for Programmers is a comprehensive introduction to the breakthrough capabilities of the new 64-bit Itanium architecture. Using standard command-line tools and extensive examples, the authors illuminate the Itanium design within the broader context of contemporary computer architecture via a step-by-step investigation of Itanium assembly language. Coverage includes: The potential of Explicitly Parallel Instruction Computing (EPIC)Itanium instruction formats and addressing modesInnovations such as the register stack engine (RSE) and extensive predicationProcedure calls and procedure-calling mechanismsFloating-point operations I/O techniques, from simple debugging to the use of filesOptimization of output from open source, Intel, and HP-UX compilers An essential resource for both computing professionals and students of architecture or assembly language, Itanium Architecture for Programmers includes extensive printed and Web-based references, plus many numeric, essay, and programming exercises for each chapter.show more

About James S. Evans

JAMES S. EVANS is Professor of Computer Science and Chemistry and Director of Information Technology Planning at Lawrence University, Appleton, WI, where he teaches courses in computer architecture, hardware organization, and operating systems. He is also lead author of Alpha RISC Architecture for Programmers (Prentice Hall PTR). He holds a Ph.D. from Princeton University.GREGORY L. TRIMPER is Principal of viika, a consultancy specializing in portable technology and field computing, software design and implementation, and project management. He holds a B.A. from Lawrence University and pursues further studies at the University of Wisconsin-Madison.show more

Table of contents

(NOTE: Each chapter concludes with Summary, References, and Exercises.) List of Figures. List of Tables. Preface. Acknowledgments. Trademarks. 1. Architecture and Implementation. Analogy: Piano Architecture. Types of Computer Languages. Why Study Assembly Language? Prefixes for Binary Multiples. Instruction Set Architectures. The Life Cycle of Computer Architectures. SQUARES: A First Programming Example. Review of Number Systems. 2. Computer Structures and Data Representations. Computer Structures. Instruction Execution. Classes of Instruction Set Architectures. Migration to 64-Bit Architectures. Itanium Information Units and Data Types. 3. The Program Assembler and Debugger. Programming Environments. Program Development Steps. Comparing Variants of a Source File. Assembler Statement Types. The Functions of a Symbolic Assembler. The Assembly Process. The Linking Process. The Program Debugger. Conventions for Writing Programs. 4. Itanium Instruction Formats and Addressing. Overview of Itanium Instruction Formats. Integer Arithmetic Instructions. Bit Encoding for Itanium Instructions. HEXNUM: Using Arithmetic Instructions. Data Access Instructions. Other ALU Instructions. DOTPROD: Using Data Access Instructions. Itanium Addressing Modes. Addressing in Other Architectures. 5. Comparison, Branches, and Predication. Hardware Basis for Control of Flow. Integer Compare Instructions. Program Branching. DOTLOOP: Using a Counted Loop. Stops, Instruction Groups, and Performance. DOTCLOOP: Using the Loop Count Register. Other Structured Programming Constructs. MAXIMUM: Using Conditional Instructions. 6. Logical Operations, Bit-Shifts, and Bytes. Logical Functions. HEXNUM2: Using Logical Masks. Bit and Field Operations. SCANTEXT: Processing Bytes. Integer Multiplication and Division. DECNUM: Converting an Integer to Decimal Format. Using C for ASCII Input and Output. BACKWARD: Using Byte Manipulations. 7. Subroutines, Procedures, and Functions. Memory Stacks. DECNUM2: Using Stack Operations. Register Stacks. Program Segmentation. Calling Conventions. DECNUM3 and BOOTH: Making a Function. Integer Quotients and Remainders. RANDOM: A Callable Function. 8. Floating-Point Operations. Parallels Between Integer and Floating-Point Instructions. Representations of Floating-Point Values. Copying Floating-Point Data. Floating-Point Arithmetic Instructions. HORNER: Evaluating a Polynomial. Predication Based on Floating-Point Values. Integer Operations in Floating-Point Execution Units. Approximations for Reciprocals and Square Roots. APPROXPI: Using Floating-Point Instructions. 9. Input and Output of Text. File Systems. Keyboard and Display I/O. SCANTERM: Using C Standard I/O. SORTSTR: Sorting Strings. Text File I/O. SCANFILE: Input and Output with Files. SORTINT: Sorting Integers from a File. Binary Files. 10. Performance Considerations. Processor-Level Parallelism. Instruction-Level Parallelism. Explicit Parallelism in the Itanium Processors. Software-Pipelined Loops. Modulo Scheduling a Loop. Program Optimization Factors. Fibonacci Numbers. 11. Looking at Output from Compilers. Compilers for RISC-like Systems. Compiling a Simple Program. Optimizing a Simple Program. Inline Optimizations. Profile-Guided or Other Optimizations. Debugging Optimized Programs. Recursion for Fibonacci Numbers Revisited. 12. Parallel Operations. Classification of Computing Systems. Integer Parallel Operations. Applications to Integer Multiplication. Opportunities and Challenges. Floating-Point Parallel Operations. Semaphore Support for Parallel Processes. 13. Variations among Implementations. Why Implementations Change. How Implementations Change. The Original Itanium Processor. A Major Role for Software. IA-32 Instruction Set Mode. Determining Extensions and Implementation Version. Appendix A: Command-Line Environments. References. Exercises. Appendix B: Suggested System Resources. System Hardware. SystemSoftware. Desktop Client Access Software. References. Appendix C: Itanium Instruction Set. C-1Instructions Listed by Function. C-2Instructions Listed by Assembler Opcode. References. Appendix D: Itanium Registers and Their Uses. Instruction Pointer. General Registers and NaT Bits. Predicate Registers. Branch Registers. Floating-Point Registers. Application Registers. State Management Registers. System Information Registers. System Control Registers. References. Appendix E: Conditional Assembly and Macros (GCC Assembler). Interference from Explicit Stops. Repeat Blocks. Conditional Assembly. Macro Processing. Using Labels with Macros. Recursive Macros. Object File Sections. MONEY: A Macro Illustrating Sections. Summary. References. Exercises. Appendix F: Inline Assembly. HP-UX C Compilers. GCC Compiler for Linux. Intel Compilers for Linux. References. Bibliography. Answers and Hints for Selected Exercises. About the Authors. Index.show more

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