Intel Xeon Phi Processor High Performance Programming

Intel Xeon Phi Processor High Performance Programming : Knights Landing Edition

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Description

This book is an all-in-one source of information for programming the Second-Generation Intel Xeon Phi product family also called Knights Landing. The authors provide detailed and timely Knights Landingspecific details, programming advice, and real-world examples. The authors distill their years of Xeon Phi programming experience coupled with insights from many expert customers - Intel Field Engineers, Application Engineers, and Technical Consulting Engineers - to create this authoritative book on the essentials of programming for Intel Xeon Phi products.

Intel (R) Xeon Phi (TM) Processor High-Performance Programming is useful even before you ever program a system with an Intel Xeon Phi processor. To help ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi processors, or other high-performance microprocessors. Applying these techniques will generally increase your program performance on any system and prepare you better for Intel Xeon Phi processors.
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Product details

  • Paperback | 662 pages
  • 191 x 235 x 30.48mm | 1,290g
  • Morgan Kaufmann Publishers In
  • San Francisco, United States
  • English
  • 2nd edition
  • 0128091940
  • 9780128091944
  • 887,966

Table of contents

Introduction
High Performance examples
Vectorization
Tasking
KNL Architecture
In-package memory
System / OS software
Math library
MPI
Profiling, tuning, power
Future offloading
Summary
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Review Text

"I believe you will find this book is an invaluable reference to help develop your own Unfair Advantage." - James A. Ang, Ph.D., Manager, Exascale Computing Program, Sandia National Laboratories, New Mexico, USA
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Review quote

"I believe you will find this book is an invaluable reference to help develop your own Unfair Advantage." - James A. Ang, Ph.D., Manager, Exascale Computing Program, Sandia National Laboratories, New Mexico, USA
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About James Jeffers

Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel (R) MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012. Avinash Sodani is the chief architect of the Knights Landing Xeon Phi Processor. He has many years of experience architecting high end processors and previously was one of the architects for the first Core(tm) processor codenamed Nehalem.
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9 ratings
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3 44% (4)
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