Hardware Design and Petri Nets

Hardware Design and Petri Nets

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Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits.
The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool.
The ever-growing demand in the electronic industry for design automation to build various types of computer-based systems creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are increasingly becoming distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages.
Hardware Design and Petri Nets is divided into five parts, which cover aspects of behavioral modelling, analysis and verification, synthesis from Petri nets and STGs, design environments based on high-level Petri nets and HDLs, and finally performance analysis using Petri nets.
Hardware Design and Petri Nets serves as an excellent reference source and may be used as a text for advanced courses on the subject.
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Product details

  • Hardback | 332 pages
  • 166.9 x 246.4 x 25.1mm | 671.33g
  • Dordrecht, Netherlands
  • English
  • 2000 ed.
  • XII, 332 p.
  • 0792377915
  • 9780792377917

Table of contents

Preface. Part I: Hardware Modelling using Petri Nets. 1. Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour; R. Wollowski, J. Beister. 2. Complementing Role Models with Petri Nets in Studying Asynchronous Data Communications; F. Xia, I. Clark. 3. Petri Net Representations of Computational and Communication Operators; D.H. Schaefer, J.H. Sosa. Part II: Model Analysis and Verification for Asynchronous Design. 4. Properties of Change Diagrams; U. Schwiegelshohn, L. Thiele. 5. LTrL-based Model Checking for a Restricted Class of Signal Transition Graphs; R. Meyer, P.S. Thiagarajan. 6. A Polynomial Algorithm to Compute the Concurrency Relation of a Regular STG; A. Kovalyov. Part III: Theory and Practice of Petri Net Based Synthesis. 7. Synthesis of Synchronous Digital Systems Specified by Petri Nets; N. Marranghello, et al. 8. Deriving Signal Transition Graphs from Behavioral Verilog HDL; I. Blunno, L. Lavagno. 9. The Design of the Control Circuits for an Asynchronous Instruction Prefetch Unit Using Signal Transition Graphs; S.-H. Chung, S. Furber. Part IV: Hardware Design Methods and Tools. 10. Electronic System Design Automation Using High Level Petri Nets; P. Rokyta, et al. 11. An Evolutionary Approach to the Use of Petri Net Based Models; R.J. Machado, et al. 12. Modelling and Implementation of Petri Nets Using VHDL; D. Prothero. Part V: Architecture Modelling and Performance Analysis. 13. Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets; A. Xie, P.A. Beerel. 14. Performance Analysis of Dataflow Architectures Using Timed Coloured Petri Nets; B.R.T.M. Witlox, et al. 15. Modeling a Memory Subsystem with Petri Nets: a Case Study; M. Gries. 16. Performance Modeling of Multithreaded Distributed Memory Architectures; W.M. Zuberek.
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