Hardware Component Modeling

Hardware Component Modeling

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The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL- based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.
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Product details

  • Hardback | 134 pages
  • 155 x 235 x 11.18mm | 880g
  • Dordrecht, Netherlands
  • English
  • 1996 ed.
  • XVIII, 134 p.
  • 0792396863
  • 9780792396864

Table of contents

Series Presentation. Editors. Volume Presentation. 1. The History of VITAL: VHDL ASIC Library Update; V. Berman. 2. Issues in Efficient Modeling and Acceleration of Vital Models; S. Nayak, A. Roy. 3. Standards for Interoperability and Portability; S. Hurat. 4. Abstract Data Types and the Digital System Description and Simulation Environments; P.A. Wilsey, et al. 5. Modeling Highly Flexible and Self-Generating Parameterizable Components in VHDL; V. Preis, S. Marz- Roessel. 6. Melody: An Efficient Layout-Based Model Generator; F. Delguste, et al. 7. Quality Measures & Analysis: A Way to Improve VHDL Models; M. Mastretti, et al. 8. Modern Concepts of Quality and Their Relationship to Design Reuse and Model Libraries; L. Jozwiak. Index.
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