A Guide to RISC Microprocessors

A Guide to RISC Microprocessors

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Description

This is a collection of articles on RISC microprocessors which appeared in "Microprocessor Report" from February 1988 through February 1991. The essays provide a technical overview with specifications, advantages and drawbacks for each chip. Features include sections on each major system: SPARC, MIPS, Motorola 88000, Intel 960, and AMD 29000. The book is intended for computer design engineers, both hardware and software.
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Product details

  • Hardback | 322 pages
  • 166.9 x 231.9 x 28.2mm | 716.67g
  • Academic Press Inc
  • San Diego, United States
  • English
  • 2nd edition
  • index
  • 0126491402
  • 9780126491401

Table of contents

Part 1 Perspective: RISC architectures, M. Slater; instruction set design, B. Case; design issues for next-generation processors, B. Case; SPARC architecture, B. Case; cypress SPARC chips, M. Slater; SPARC support, M. Slater; redesigned cypress SPARC chips, M. Slater; first ECL microprocessor, M. Slater; LSI logic embedded control SPARC processor, M. Slater; fujitsu embedded SPARC processor, M. Slater. Part 2 MIPS: MIPS processor, M. Slater; MIPS R3000 system design, M. Slater; IDT R3000 derivative, M. Slater; MIPS chip set with full ECL CPU implementation, M. Slater; ECL bus controller, M. Thorson; IDT embedded MIPS processors, M. Slater; high integration on MIPS based processor, M. Slater; MIPS with 64-Bit R4000 architecture. Part 3 Motorola 88000: motorola 88000 RISC chip set, M. Slater;Motorola 88200, M. Slater. Part 5 Intel 960: intel register scoreboarding, J.H. Wharton; intel 960 architecture, J.H. Wharton; intel i860 performance, B. Case; intel i860 parallel processing support, M. Slater; MASS860, B. Case and M. Slater. Part 6 AMD 29000: AMD 29000 architecture, B. Case; AMD 29000 bus structure, B. Case and T. Olson; AMD 29050, B. Case; PA-RISC, B. Case; PA workstations, M. Slater.
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