Formal Verification

Formal Verification : An Essential Toolkit for Modern VLSI Design

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Description

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
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Product details

  • Paperback | 408 pages
  • 191 x 235 x 28mm | 505g
  • Morgan Kaufmann Publishers In
  • San Francisco, United States
  • English
  • 0128007273
  • 9780128007273
  • 1,258,083

Table of contents

Formal Verification: From Dreams to Reality
Basic Formal Verification Algorithms
Introduction to SystemVerilog Assertions
Formal Property Verification
Effective FPV For Design Exercise
Effective FPV for Verification
FPV "Apps" for Specific SOC Problems
Formal Equivalence Verification
Formal Verification's Greatest Bloopers: The Danger of False Positives
Dealing with Complexity
Your New FV-Aware Lifestyle
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Review Text

"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..." -- VerificationAcademy.com
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Review quote

"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..." --VerificationAcademy.com
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About Erik Seligman

Erik has worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. Currently he works in the Design Technology and Solutions division, where he supports formal verification usage for Intel teams worldwide. In his spare time he hosts the "Math Mutation" podcast, and serves as an elected director on the Hillsboro school board. Tom recently joined the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. Kiran has been working at intel India for past 11 years and has worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of verification including formal verification. Currently he leads the formal verification efforts for the graphics design in Visual Platform Group and supports formal verification at intel india site.
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