Formal Semantics and Proof Techniques for Optimizing VHDL Models
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Formal Semantics and Proof Techniques for Optimizing VHDL Models

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Description

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
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Product details

  • Hardback | 158 pages
  • 160 x 236.2 x 17.8mm | 362.87g
  • Dordrecht, Netherlands
  • English
  • 1999 ed.
  • XXI, 158 p.
  • 0792383753
  • 9780792383758

Table of contents

1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.
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