Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories

Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories

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Description

This book deals with primarily with reliable and faul-tolerant circuit design and evaluation techniques for RAMS. It examines both the manufacturing faul-tolerance (e.g. self-repair at the time of manufacturing) and online and field-related fault-tolerance (e.g. error-correction). It talks a lot about important techniques and requirements, and explains what needs to be done and why for each of the techniques.
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Product details

  • Hardback | 448 pages
  • 182.4 x 242.3 x 22.6mm | 830.09g
  • Prentice Hall
  • Upper Saddle River, United States
  • English
  • 0130084654
  • 9780130084651

Table of contents

(NOTE: Each chapter begins with an Introduction and concludes with Concluding Remarks and Problems except for Chapter 1.)Preface. Acknowledgments. 1. Reliability and Fault Tolerance of RAMs. Impact of Scaling on Reliability. Defects, Faults, Errors, and Reliability. Reliability and Quality Testing and Measurement. Reliability Characterization. Reliability Prediction Procedures. Reliability Simulation Tools. Mechanisms for Permanent Device Failure. Safeguarding against Failures.2. Diagnosis, Repair, and Reconfiguration. Diagnosis Algorithms. Repair Algorithms. Reconfiguration Techniques. Repair Using Flash Eeprom Switches. Flexible Redundancy. Built-In Self-Diagnosis and Self-Repair. Built-In Redundancy Analysis. Built-In Self-Repair Architectures.3. Single-Event Effects and Their Mitigation. Particles Causing Single-Event Effects. Some Definitions. Basic Mechanisms for Nondestructive Single-Event Effects. RAM Device Operation. Critical Charge and Soft Error Rate. Techniques Used for Mitigation of Single-Event Upsets. Experiments. Modeling and Simulation of Charge Collection. Basic Mechanisms for Destructive Single-Event Effects.4. Error-Correcting Codes. Theory of Error-Correcting Codes. Fault-Tolerant Design Techniques for RAMs. Ecc Implementations. Memory Reliability Evaluation through Error Correction. Simulation of Memory Reliability and Fault Tolerance.5. Yield Modeling and Prediction Techniques. Yield Models. Yield Loss Mechanisms. Importance of Clustering Models. Critical Area Simulation and Yield Calculation. Effect of Redundancy and Error Correction on Yield. Effect of Defect Density on Yield. Effect of Defect Characteristics on Yield. Effect of Device Scaling on Yield. Relationship between Yield and Reliability.6. Physical Design of Built-In Self-Repairable RAMs. Embedded RAMs. Built-In Self-Repairable Embedded RAM Physical Design. Fault Modeling Based on Inductive Fault Analysis. Circuit Implementation. Characterization of a Custom Design Tool. Multiobjective Optimization Approach for RAM Design. Floorplanning of Parametrized Rectangular Macrocells. BIST/BISR for Other Types of Memories.Bibliography. Index.
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About Pinaki Mazumder

KANAD CHAKRABORTY is currently Member of Technical Staff, Agere Systems Research (Communications Systems Technology Lab). He was formerly a software engineer and researcher with IBM's Electronic Design Automation Lab. His contributions include development of novel fault-tolerant memory architectures, algorithms for multiport memory testing, new design automation approaches, and neural network applications. PINAKI MAZUMDER is Professor in the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. His research interests include nanoelectronic and quantum electronic circuits and simulation, digital and analog testing, VLSI system design, and VLSI Layout Automation. He is a Fellow of IEEE. Mazumder and Chakraborty are co-authors of Testing and Testable Design of High-Density Random-Access Memories.
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