Digital Electronics Laboratory Experiments Using the Xilinx XC95108 CPLD with Xilinx Foundation : Design and Simulation Software
For freshman/sophomore-level courses in Digital Circuit Design, Digital System Design, and Computer Engineering Technology.This manual offers an easy-to-read, easy-to-follow approach to digital fundamentals through the use of Complex Programmable Logic Devices (CPLDs). The first shorter section of the book contains a set of lab jobs using a single TTL chip: the 74LS00 quad 2-input NAND gate, allowing students to build a few simple circuits immediately. The second section contains a set of hands-on lab jobs with step-by-step instructions on using the Xilinx XC95108 CPLD. The use of advanced logic device technology in an introductory digital course prepares students both for lab work in advanced courses as well as for using an industry-standard design environment.
- Paperback | 320 pages
- 210 x 272 x 18mm | 598.75g
- 27 Apr 2003
- Pearson Education (US)
- Upper Saddle River, NJ, United States
- 2nd edition
Table of contents
I. TTL EXPERIMENTS. Experiment 1. Basic Gates 1: AND, NOT, NAND. Experiment 2. Basic Gates 2: OR, NOR. Experiment 3. A Combinational Circuit. Experiment 4. The Cross-Coupled Latch & Switch De-Bouncing. II. CPLD EXPERIMENTS. Experiment 1. AND Gates & OR Gates. Experiment 2. Inverting Logic: NOT, NAND, & NOR. Experiment 3. Boolean Laws, Rules, & DeMorgan's Theorem. Experiment 4. XOR & XNOR Gates with Applications. Experiment 5. Use of XOR/XNOR Gates to Generate & Check Parity. Experiment 6. Karnaugh Maps. Experiment 7. Binary Adders. Experiment 8. Decoders & Applications. Experiment 9. Encoders & Application to a 7-Segment Display Driver. Experiment 10. Multiplexers & Demultiplexers. Experiment 11. Latches: S-R & D-Type. Experiment 12. Flip-Flops: J-K & D-Type. Experiment 13. Asynchronous Counters. Experiment 14. TTL-Equivalent Library Counters. Experiment 15. Sequential Design in HDL: A Synchronous Counter. Experiment 16. Shift Registers & Ring Counters. Experiment 17. Sequential Design in HDL: Registers. Experiment 18. Timing Circuits: Oscillators & One-Shots. Experiment 19. Digital to Analog Converter. Experiment 20. Analog to Digital Converter. Experiment 21. The 256x8 RAM Module. Appendix A: References. Appendix B: Glossary. Appendix C: Parallel Ports. Appendix D: 74LS00 TTL Data Sheet. Appendix E: PLDT-3 User's Manual. Appendix F: XESS Data Sheet.