Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

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This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im- plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.
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Product details

  • Hardback | 112 pages
  • 176.3 x 230.6 x 13.2mm | 349.27g
  • Dordrecht, Netherlands
  • English
  • 2001 ed.
  • XIX, 112 p.
  • 079237407X
  • 9780792374077

Table of contents

Contents. List of Figures. List of Tables. Preface. Acknowledgments. Introduction; Sunil P Khatri. 1. Introduction. 2. Validating Deep Sub-Micron Effects. 3. VLSI Layout Fabrics. 4. Fabric I - Fabric Cell Based Design. 5. Fabric 3 - Network of PLA Based Design. 6. Wire Removal in a Network of PLAS. 7. Conclusions and Future Directions. Appendices. Index.
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