CMOS/BiCMOS ULSI : Low Voltage, Low Power

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For upper level and graduate level Electrical and Computer Engineering courses in Integrated Circuit Design as well as professional circuit designers, engineers and researchers working in portable wireless communications hardware.

This book presents the fundamentals of Complementary Metal Oxide Semiconductor (CMOS) and Bipolar compatible Complementary Metal Oxide Semiconductor (BiCMOS) technology, as well as the latest technological advances in the field. It discusses the concepts and techniques of new integrated circuit design for building high performance and low power circuits and systems for current and future very-large-scale-integration (VLSI) and giga-scale-integration (GSI) applications. CMOS/BiCMOS ULSI: Low-Voltage Low-Power is an essential resource for every professional moving toward lower voltage, lower power, and higher performance VLSI circuits and subsystems design.
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Product details

  • Hardback | 624 pages
  • 187.5 x 240.3 x 35.1mm | 1,088.63g
  • Prentice Hall
  • Upper Saddle River, United States
  • English
  • 0130321621
  • 9780130321626

Table of contents

(NOTE: Each chapter begins with an Introduction and concludes with References.).




1. Introduction.

Low-Power Design: An Overview. Low-Voltage, Low-Power Design Limitations. Silicon-On-Insulator (SOI). From Devices to Circuits.

2. MOS/BiCMOS Process Technology and Integration.

The Realization of BiCMOS Processes. BiCMOS Manufacturing and Integration Considerations. Isolation in BiCMOS. Integrated Analog/Digital BiCMOS Process. Deep Submicron Processes. Low-Voltage/Low-Power CMOS/BiCMOS Processes. Future Trends and Directions of CMOS/BiCMOS Processes. Conclusions.

3. Device Behavior and Modeling.

The MOS(FET) Transistor. The Bipolar (Junction) Transistor. The Bipolar (Junction) Transistor. MOSFET SPICE Models. Advanced MOSFET Models. Advanced MOSFET Models. Bipolar SPICE Models. Bipolar SPICE Models. Bipolar SPICE Models. The MOSFET in a Hybrid-Mode Environment. Summary.

4. Low-Voltage, Low-Power Logic Circuits.

Conventional CMOS Logic Gates. Conventional BiCMOS Logic Gate. BiCMOS Circuits Utilizing Lateral pnp BJTs in pMOS Structures. Merged BiCMOS Digital Circuits. Full-Swing Multidrain/Multicollector Complementary BiCMOS Buffers. Quasi-Complementary BiCMOS Digital Circuits. Full-Swing BiCMOS/BiNMOS Digital Circuits Employing Schottky Diodes. Feedback-Type BiCMOS Digital Circuits. High-Beta BiCMOS Digital Circuits. Transiently Saturated Full-Swing BiCMOS Digital Circuits. Transiently Saturated Full-Swing BiCMOS Digital Circuits. Bootstrapped-Type BiCMOS Digital Circuits. ESD-Free BiCMOS Digital Circuit. Conclusion.

5. Low-Power Latches and Flip-Flops.

Evolution of Latches and Flip-Flops. Quality Measures for Latches and Flip-Flops. Latches and Flip-Flops: A Design Perspective.

A. Basic Equations.

Current Equations. Charge Equations. Noise Equations. Parameter Scaling (Geometrical scaling and temperature scaling).

B. Model Equations.

DC Current Model. Charge Model. Noise Model.

C. Hyperbolic (HYP) Functions.

D. JUNCAP Model.

Temperature, Geometry, and Voltage Dependence. JUNCAPCapacitor and Leakage Current Model.


About the Authors.
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About Kiat-Seng Yeo

KIAT-SENG YEO joined the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore in 1993. He is now the Sub-Dean of EEE, Principal Investigator of NTU's Integrated Circuit Technology Research Group, Program Manager of the System-on-Chip Flagship Project, Coordinator of the Integrated Circuit Design Research Group, Technical Chairman of the 8th and 9th International Symposium on Integrated Circuits, Devices and Systems, and a Technical Consultant. He holds six patents and published more than 100 articles in BiCMOS/CMOS integrated circuit design and technology.

SAMIR S. ROFAIL has been a teacher, researcher, and consultant in semiconductor and IC design for 20 years. From 1992 to 1999, he coordinated NTU's IC-Design group, leading intensive research on low-voltage, low-power BiCMOS/CMOS circuits. He is now a technical consultant in Waterloo, Canada.

WANG-LING GOH joined NTU in 1996. Her research interests are in the areas of silicon processing technologies, particularly the SOI structures, CMP and Copper. She holds one patent and has published over 30 articles in the above named areas.
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