The Art of Analog Layout

The Art of Analog Layout : International Edition

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For Electrical Engineering courses in analog layout or professional layout designers. This text covers the issues involved in successfully laying out analog integrated circuits. Hastings provides clear guidance and does not stress theoretical physics or mathematical analysis of layouts. He emphasizes cross- sections of devices and carrier-based models of device operation as compared to the more common geometric and schematic representation of devices.show more

Product details

  • Paperback | 672 pages
  • 203 x 255 x 30mm | 1,212g
  • Pearson Education (US)
  • Pearson
  • United States
  • English
  • 2nd edition
  • 013129329X
  • 9780131293298

Table of contents

Preface to the Second Edition xviiPreface to the First Edition xixAcknowledgments xxi1 Device Physics 11.1 Semiconductors 11.1.1. Generation and Recombination 41.1.2. Extrinsic Semiconductors 61.1.3. Diffusion and Drift 91.2 PN Junctions 111.2.1. Depletion Regions 111.2.2. PN Diodes 131.2.3. Schottky Diodes 161.2.4. Zener Diodes 181.2.5. Ohmic Contacts 191.3 Bipolar Junction Transistors 211.3.1. Beta 231.3.2. I-V Characteristics 241.4 MOS Transistors 251.4.1. Threshold Voltage 271.4.2. I-V Characteristics 291.5 JFET Transistors 321.6 Summary 341.7 Exercises 352 Semiconductor Fabrication 372.1 Silicon Manufacture 372.1.1. Crystal Growth 382.1.2. Wafer Manufacturing 392.1.3. The Crystal Structure of Silicon 392.2 Photolithography 412.2.1. Photoresists 412.2.2. Photomasks and Reticles 422.2.3. Patterning 432.3 Oxide Growth and Removal 432.3.1. Oxide Growth and Deposition 442.3.2. Oxide Removal 452.3.3. Other Effects of Oxide Growth and Removal 472.3.4. Local Oxidation of Silicon (LOCOS) 492.4 Diffusion and Ion Implantation 502.4.1. Diffusion 512.4.2. Other Effects of Diffusion 532.4.3. Ion Implantation 552.5 Silicon Deposition and Etching 572.5.1. Epitaxy 572.5.2. Polysilicon Deposition 592.5.3. Dielectric Isolation 602.6 Metallization 622.6.1. Deposition and Removal of Aluminum 632.6.2. Refractory Barrier Metal 652.6.3. Silicidation 672.6.4. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat 692.6.5. Copper Metallization 712.7 Assembly 732.7.1. Mount and Bond 742.7.2. Packaging 772.8 Summary 782.9 Exercises 783 Representative Processes 803.1 Standard Bipolar 813.1.1. Essential Features 813.1.2. Fabrication Sequence 82Starting Material 82N-Buried Layer 82Epitaxial Growth 83Isolation Diffusion 8383Base Implant 84Emitter Diffusion 84Contact 85Metallization 85Protective Overcoat 863.1.3. Available Devices 86NPN Transistors 86PNP Transistors 88Resistors 90Capacitors 923.1.4. Process Extensions 93Up-Down Isolation 93Double-Level Metal 94Schottky Diodes 94High-Sheet Resistors 94Super-Beta Transistors 963.2 Polysilicon-Gate CMOS 963.2.1. Essential Features 973.2.2. Fabrication Sequence 98Starting Material 98Epitaxial Growth 98N-Well Diffusion 98Inverse Moat 99Channel Stop Implants 100LOCOS Processing and Dummy Gate Oxidation 100Threshold Adjust 101Deep-N+Polysilicon Deposition and Patterning 102Source/Drain Implants 102Contacts 103Metallization 103Protective Overcoat 1033.2.3. Available Devices 104NMOS Transistors 104PMOS Transistors 106Substrate PNP Transistors 107Resistors 107Capacitors 1093.2.4. Process Extensions 109Double-Level Metal 110Shallow Trench Isolation 110Silicidation 111Lightly Doped Drain (LDD) Transistors 112Extended-Drain, High-Voltage Transistors 1133.3 Analog BiCMOS 1143.3.1. Essential Features 1153.3.2. Fabrication Sequence 116Starting Material 116N-Buried Layer 116Epitaxial Growth 117N-Well Diffusion and 117Base Implant 118Inverse Moat 118Channel Stop Implants 119LOCOS Processing and Dummy Gate Oxidation 119Threshold Adjust 119Polysilicon Deposition and Pattern 120Source/Drain Implants 120Metallization and Protective Overcoat 120Process Comparison 1213.3.3. Available Devices 121NPN Transistors 121PNP Transistors 123Resistors 1253.3.4. Process Extensions 125Advanced Metal Systems 126Dielectric Isolation 1263.4 Summary 1303.5 Exercises 1314 Failure Mechanisms 1334.1 Electrical Overstress 1334.1.1. Electrostatic Discharge (ESD) 134Effects 135Preventative Measures 1354.1.2. Electromigration 136Effects 136Preventative Measures 137Deep-N+4.1.3. Dielectric Breakdown 138Effects 138Preventative Measures 1394.1.4. The Antenna Effect 141Effects 141Preventative Measures 1424.2 Contamination 1434.2.1. Dry Corrosion 144Effects 144Preventative Measures 1454.2.2. Mobile Ion Contamination 145Effects 145Preventative Measures 1464.3 Surface Effects 1484.3.1. Hot Carrier Injection 148Effects 148Preventative Measures 1504.3.2. Zener Walkout 151Effects 151Preventative Measures 1524.3.3. Avalanche-Induced Beta Degradation 153Effects 153Preventative Measures 1544.3.4. Negative Bias Temperature Instability 154Effects 155Preventative Measures 1554.3.5. Parasitic Channels and Charge Spreading 156Effects 156Preventative Measures (Standard Bipolar) 159Preventative Measures (CMOS and BiCMOS) 1624.4 Parasitics 1644.4.1. Substrate Debiasing 165Effects 166Preventative Measures 1674.4.2. Minority-Carrier Injection 169Effects 169Preventative Measures (Substrate Injection) 172Preventative Measures (Cross-Injection) 1784.4.3. Substrate Influence 180Effects 180Preventative Measures 1804.5 Summary 1834.6 Exercises 1835 Resistors 1855.1 Resistivity and Sheet Resistance 1855.2 Resistor Layout 1875.3 Resistor Variability 1915.3.1. Process Variation 1915.3.2. Temperature Variation 1925.3.3. Nonlinearity 1935.3.4. Contact Resistance 1965.4 Resistor Parasitics 1975.5 Comparison of Available Resistors 2005.5.1. Base Resistors 2005.5.2. Emitter Resistors 2015.5.3. Base Pinch Resistors 2025.5.4. High-Sheet Resistors 2025.5.5. Epi Pinch Resistors 2055.5.6. Metal Resistors 2065.5.7. Poly Resistors 2085.5.8. NSD and PSD Resistors 2115.5.9. N-Well Resistors 2115.5.10. Thin-Film Resistors 2125.6 Adjusting Resistor Values 2135.6.1. Tweaking Resistors 213Sliding Contacts 214Sliding Heads 215Trombone Slides 215Metal Options 2155.6.2. Trimming Resistors 216Fuses 216Zener Zaps 219EPROM Trims 221Laser Trims 2225.7 Summary 2235.8 Exercises 2246 Capacitors and Inductors 2266.1 Capacitance 2266.1.1. Capacitor Variability 232Process Variation 232Voltage Modulation and Temperature Variation 2336.1.2. Capacitor Parasitics 2356.1.3. Comparison of Available Capacitors 237Base-Emitter Junction Capacitors 237MOS Capacitors 239Poly-Poly Capacitors 241Stack Capacitors 243Lateral Flux Capacitors 245High-Permittivity Capacitors 2466.2 Inductance 2466.2.1. Inductor Parasitics 2486.2.2. Inductor Construction 250Guidelines for Integrating Inductors 2516.3 Summary 2526.4 Exercises 2537 Matching of Resistors and Capacitors 2547.1 Measuring Mismatch 2547.2 Causes of Mismatch 2577.2.1. Random Variation 257Capacitors 258Resistors 2587.2.2. Process Biases 2607.2.3. Interconnection Parasitics 2617.2.4. Pattern Shift 2637.2.5. Etch Rate Variations 2657.2.6. Photolithographic Effects 2677.2.7. Diffusion Interactions 2687.2.8. Hydrogenation 2707.2.9. Mechanical Stress and Package Shift 2717.2.10. Stress Gradients 274Piezoresistivity 274Gradients and Centroids 275Common-Centroid Layout 277Location and Orientation 2817.2.11. Temperature Gradients and Thermoelectrics 283Thermal Gradients 285Thermoelectric Effects 2877.2.12. Electrostatic Interactions 288Voltage Modulation 288Charge Spreading 292Dielectric Polarization 293Dielectric Relaxation 2947.3 Rules for Device Matching 2957.3.1. Rules for Resistor Matching 2967.3.2. Rules for Capacitor Matching 3007.4 Summary 3037.5 Exercises 3048 Bipolar Transistors 3068.1 Topics in Bipolar Transistor Operation 3068.1.1. Beta Rolloff 3088.1.2. Avalanche Breakdown 3088.1.3. Thermal Runaway and Secondary Breakdown 3108.1.4. Saturation in NPN Transistors 3128.1.5. Saturation in Lateral PNP Transistors 3158.1.6. Parasitics of Bipolar Transistors 3188.2 Standard Bipolar Small-Signal Transistors 3208.2.1. The Standard Bipolar NPN Transistor 320Construction of Small-Signal NPN Transistors 3228.2.2. The Standard Bipolar Substrate PNP Transistor 326Construction of Small-Signal Substrate PNP Transistors 3288.2.3. The Standard Bipolar Lateral PNP Transistor 330Construction of Small-Signal Lateral PNP Transistors 3328.2.4. High-Voltage Bipolar Transistors 3378.2.5. Super-Beta NPN Transistors 3408.3 CMOS and BiCMOS Small-Signal Bipolar Transistors 3418.3.1. CMOS PNP Transistors 3418.3.2. Shallow-Well Transistors 3458.3.3. Analog BiCMOS Bipolar Transistors 3478.3.4. Fast Bipolar Transistors 3498.3.5. Polysilicon-Emitter Transistors 3518.3.6. Oxide-Isolated Transistors 3548.3.7. Silicon-Germanium Transistors 3568.4 Summary 3588.5 Exercises 3589 Applications of Bipolar Transistors 3609.1 Power Bipolar Transistors 3619.1.1. Failure Mechanisms of NPN Power Transistors 362Emitter Debiasing 362Thermal Runaway and Secondary Breakdown 364Kirk Effect 3669.1.2. Layout of Power NPN Transistors 368The Interdigitated-Emitter Transistor 369The Wide-Emitter Narrow-Contact Transistor 371The Christmas-Tree Device 372The Cruciform-Emitter Transistor 373Power Transistor Layout in Analog BiCMOS 374Selecting a Power Transistor Layout 3769.1.3. Power PNP Transistors 3769.1.4. Saturation Detection and Limiting 3789.2 Matching Bipolar Transistors 3819.2.1. Random Variations 3829.2.2. Emitter Degeneration 3849.2.3. NBL Shadow 3869.2.4. Thermal Gradients 3879.2.5. Stress Gradients 3919.2.6. Filler-Induced Stress 3939.2.7. Other Causes of Systomatic Mismatch 3959.3 Rules for Bipolar Transistor Matching 3969.3.1. Rules for Matching Vertical Transistors 3979.3.2. Rules for Matching Lateral Transistors 4029.4 Summary 4029.5 Exercises 40310 Diodes 40610.1 Diodes in Standard Bipolar 40610.1.1. Diode-Connected Transistors 40610.1.2. Zener Diodes 409Surface Zener Diodes 410Buried Zeners 41210.1.3. Schottky Diodes 41510.1.4. Power Diodes 42010.2 Diodes in CMOS and BiCMOS Processes 42210.2.1. CMOS Junction Diodes 42210.2.2. CMOS and BiCMOS Schottky Diodes 42310.3 Matching Diodes 42510.3.1. Matching PN Junction Diodes 42510.3.2. Matching Zener Diodes 42610.3.3. Matching Schottky Diodes 42810.4 Summary 42810.5 Exercises 42911 Field-Effect Transistors 43011.1 Topics in MOS Transistor Operation 43111.1.1. Modeling the MOS Transistor 431Device Transconductance 432Threshold Voltage 43411.1.2. Parasitics of MOS Transistors 438Breakdown Mechanisms 440CMOS Latchup 442Leakage Mechanisms 44311.2 Constructing CMOS Transistors 44611.2.1. Coding the MOS Transistor 447Width and Length 44811.2.2. N-Well and P-Well Processes 44911.2.3. Channel Stop Implants 45211.2.4. Threshold Adjust Implants 45311.2.5. Scaling the Transistor 45611.2.6. Variant Structures 459Serpentine Transistors 461Annular Transistors 46211.2.7. Backgate Contacts 46411.3 Floating-Gate Transistors 46711.3.1. Principles of Floating-Gate Transistor Operation 46911.3.2. Single-Poly EEPROM Memory 47211.4 The JFET Transistor 47411.4.1. Modeling the JFET 47411.4.2. JFET Layout 47611.5 Summary 47911.6 Exercises 47912 Applications of MOS Transistors 48212.1 Extended-Voltage Transistors 48212.1.1. LDD and DDD Transistors 48312.1.2. Extended-Drain Transistors 486Extended-Drain NMOS Transistors 487Extended-Drain PMOS Transistors 48812.1.3. Multiple Gate Oxides 48912.2 Power MOS Transistors 49112.2.1. MOS Safe Operating Area 492Electrical SOA 493Electrothermal SOA 496Rapid Transient Overload 49712.2.2. Conventional MOS Power Transistors 498The Rectangular Device 499The Diagonal Device 500Computation of 501 RMOther Considerations 502Nonconventional Structures 50312.2.3. DMOS Transistors 505The Lateral DMOS Transistor 506RESURF Transistors 508The DMOS NPN 51012.3 MOS Transistor Matching 51112.3.1. Geometric Effects 513Gate Area 513Gate Oxide Thickness 514Channel Length Modulation 515Orientation 51512.3.2. Diffusion and Etch Effects 516Polysilicon Etch Rate Variations 516Diffusion Penetration of Polysilicon 517Contacts Over Active Gate 518Diffusions Near the Channel 518PMOS versus NMOS Transistors 51912.3.3. Hydrogenation 520Fill Metal and MOS Matching 52112.3.4. Thermal and Stress Effects 521Oxide Thickness Gradients 522Stress Gradients 522Thermal Gradients 52212.3.5. Common-Centroid Layout of MOS Transistors 52312.4 Rules for MOS Transistor Matching 52812.5 Summary 53112.6 Exercises 53113 Special Topics 53413.1 Merged Devices 53413.1.1. Flawed Device Mergers 53513.1.2. Successful Device Mergers 53913.1.3. Low-Risk Merged Devices 54113.1.4. Medium-Risk Merged Devices 54213.1.5. Devising New Merged Devices 54413.1.6. The Role of Merged Devices in Analog BiCMOS 54413.2 Guard Rings 54513.2.1. Standard Bipolar Electron Guard Rings 54613.2.2. Standard Bipolar Hole Guard Rings 54713.2.3. Guard Rings in CMOS and BiCMOS Designs 54813.3 Single-level Interconnection 55113.3.1. Mock Layouts and Stick Diagrams 55113.3.2. Techniques for Crossing Leads 55313.3.3. Types of Tunnels 55513.4 Constructing the Padring 55713.4.1. Scribe Streets and Alignment Markers 55713.4.2. Bondpads,Trimpads, and Testpads 55813.5 ESD Structures 56213.5.1. Zener Clamp 56313.5.2. Two-Stage Zener Clamps 56513.5.3. Buffered Zener Clamp 56613.5.4. Clamp 56813.5.5. Clamp 56913.5.6. Antiparallel Diode Clamps 57013.5.7. Grounded-Gate NMOS Clamps 57013.5.8. CDM Clamps 57213.5.9. Lateral SCR Clamps 57313.5.10. Selecting ESD Structures 57513.6 Exercises 57814 Assembling the Die 58114.1 Die Planning 58114.1.1. Cell Area Estimation 582Resistors 582Capacitors 582Vertical Bipolar Transistors 583Lateral PNP Transistors 583MOS Transistors 583MOS Power Transistors 584Computing Cell Area 58414.1.2. Die Area Estimation 58414.1.3. Gross Profit Margin 58714.2 Floorplanning 58814.3 Top-Level Interconnection 59414.3.1. Principles of Channel Routing 59414.3.2. Special Routing Techniques 596Kelvin Connections 597Noisy Signals and Sensitive Signals 59814.3.3. Electromigration 60014.3.4. Minimizing Stress Effects 60314.4 Conclusion 60414.5 Exercises 605AppendicesA. Table of Acronyms Used in the Text 607B. The Miller Indices of a Cubic Crystal 611C. Sample Layout Rules 614D. Mathematical Derivations 622E. Sources for Layout Editor Software 627Index 628show more

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