The Art of Analog Layout

The Art of Analog Layout

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For courses in Analog Layout. The first textbook in the field. This text provides students with a broad understanding of the issues involved in successfully laying out analog integrated circuits-ranging from the mechanics of layout to essential information about many related areas, such as device physics, processing, failure modes and effects, device operation, parasitics, and matching. It emphasizes practical more

Product details

  • Hardback | 539 pages
  • 203.2 x 262.6 x 26.9mm | 1,197.49g
  • Pearson Education Limited
  • Prentice-Hall
  • Harlow, United Kingdom
  • 0130870617
  • 9780130870612

Table of contents

(NOTE: Each chapter concludes with "Summary" and "Exercises.") 1. Device Physics. Semiconductors. Generation and Recombination. Extrinsic Semiconductors. Diffusion and Drift. PN Junctions. Depletion Regions. PH Diodes. Schottky Diodes. Zener Diodes. Ohmic Contacts. Bipolar Junction Transistors. Beta. I-V Characteristics. MOS Transistors. Threshold Voltage. I-V Characteristics. JFET Transistors. 2. Semiconductor Fabrication. Silicon Manufacture. Crystal Growth. Wafer Manufacturing. The Crystal Structure of Silicon. Photolithography. Photoresists. Photomasks and Reticles. Patterning. Oxide Growth and Removal. Oxide Growth and Deposition. Oxide Removal. Other Effects of Oxide Growth and Removal. Local Oxidation of Silicon (LOCOS). Diffusion and Ion Implantation. Diffusion. Other Effects of Diffusion. Ion Implantation. Silicon Deposition. Epitaxy. Polysilicon Deposition. Metallization. Deposition and Removal of Aluminum. Refractory Barrier Metal. Silicidation. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat. Assembly. Mount and Bond. Packaging. 3. Representative Processes. Standard Bipolar. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Polysilicon-Gate CMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Analog BiCMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. 4. Failure Mechanisms. Electrical Overstress. Electrostatic Discharge (ESD). Electromigration. The Antenna Effect. Contamination. Dry Corrosion. Mobile Ion Contamination. Surface Effects. Hot Carrier Injection. Parasitic Channels and Charge Spreading. Parasitics. Substrate Debiasing. Minority-Carrier Injection. 5. Resistors. Resistivity and Sheet Resistance. Resistor Layout. Resistor Variability. Process Variation. Temperature Variation. Nonlinearity. Contact Resistance. Resistor Parasitics. Comparison of Available Resistors. Base Resistors. Emitter Resistors. Base Pinch Resistors. High-Sheet Resistors. Epi Pinch Resistors. Metal Resistors. Poly Resistors. NSD and PSD Resistors. N-Well Resistors. Thin-Film Resistors. Adjusting Resistor Values. Tweaking Resistors. Trimming Resistors. 6. Capacitors. Capacitance. Capacitor Variability. Process Variation. Voltage Modulation and Temperature Variation. Capacitor Parasitics. Comparison of Available Capacitors. Base-Emitter Junction Capacitors. MOS Capacitors. Poly-Poly Capacitors. Miscellaneous Styles of Capacitors. 7. Matching of Resistors and Capacitors. Measuring Mismatch. Causes of Mismatch. Random Statistical Fluctuations. Process Biases. Pattern Shift. Variations in Polysilicon Etch Rate. Diffusion Interactions. Stress Gradients and Package Shifts. Temperature Gradients and Thermoelectrics. Electrostatic Interactions. Rules for Device Matching. Rules for Resistor Matching. Rules for Capacitor Matching. 8. Bipolar Transistors. Topics in Bipolar Transistor Operation. Beta Rolloff. Avalanche Breakdown. Thermal Runaway and Secondary Breakdown. Saturation in NPN Transistors. Saturation in Lateral PNP Transistors. Parasitics of Bipolar Transistors. Standard Bipolar Small-Signal Transistors. The Standard Bipolar NPN Transistor. The Standard Bipolar Substrate PNP Transistor. The Standard Bipolar Lateral PNP Transistor. High-Voltage Bipolar Transistors. Alternative Small-Signal Bipolar Transistors. Extensions to Standard Bipolar. Bipolar Transistors in a CMOS Process. Advanced-Technology Bipolar Transistors. 9. Applications of Bipolar Transistors. Power Bipolar Transistors. Failure Mechanisms of NPN Power Transistors. Layout of Power NPN Transistors. Saturation Detection and Limiting. Matching Bipolar Transistors. Random Variations. Emitter Degeneration. NBL Shadow. Thermal Gradients. Stress Gradients. Rules for Bipolar Transistor Matching. Rules for Matching NPN Transistors. Rules for Matching Lateral PNP Transistors. 10. Diodes. Diodes in Standard Bipolar. Diode-Connected Transistors. Zener Diodes. Schottky Diodes. Diodes in CMOS and BiCMOS Processes. Matching Diodes. Matching PN Junction Diodes. Matching Zener Diodes. Matching Schottky Diodes. 11. MOS Transistors. Topics in MOS Transistor Operation. Modeling the MOS Transistor. Parasitics of MOS Transistors. Self-Aligned Poly-Gate CMOS Transistors. Coding the MOS Transistor. N-Well and P-Well Processes. Channel Stops. Threshold Adjust Implants. Scaling the Transistor. Variant Structures. Backgate Contacts. 12. Applications of MOS Transistors. Extended-Voltage Transistors. LDD and DDD Transistors. Extended-Drain Transistors. Multiple Gate Oxides. Power MOS Transistors. Conventional MOS Power Transistors. DMOS Transistors. The JFET Transistor. Modeling the JFET. JFET Layout. MOS Transistor Matching. Geometric Effects. Diffusion and Etch Effects. Thermal and Stress Effects. Common-Centroid Layout of MOS Transistors. Rules for MOS Transistor Matching. 13. Special Topics. Merged Devices. Flawed Device Mergers. Successful Device Mergers. Low-Risk Merged Devices. Medium-Risk Merged Devices. Devising New Merged Devices. Guard Rings. Standard Bipolar Electron Guard Rings. Standard Bipolar Hole Guard Rings. Guard Rings in CMOS and BiCMOS Designs. Single-Level Interconnection. Mock Layouts and Stick Diagrams. Techniques for Crossing Leads. Types of Tunnels. Constructing the Padring. Scribe Streets and Alignment Markers. Bondpads, Trimpads, and Testpads. ESD Structures. Selecting ESD Structures. 14. Assembling the Die. Die Planning. Cell Area Estimation. Die Area Estimation. Gross Profit Margin. Floorplanning. Top-Level Interconnection. Principles of Channel Routing. Special Routing Techniques. Electromigration. Minimizing Stress Effects. Appendix A: Table of Acronyms Used in the Text. Appendix B: The Miller Indices of a Cubic Crystal. Appendix C: Sample Layout Rules. Appendix D: Mathematical Derivations. Appendix E: Sources for Layout Editor Software. more

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