ASIC System Design with VHDL: A Paradigm

ASIC System Design with VHDL: A Paradigm

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Description

Beginning in the mid 1980's, VLSI technology had begun to advance in two directions. Pushing the limit of integration, ULSI (Ultra Large Scale Integration) represents the frontier of the semiconductor processing technology in the campaign to conquer the submicron realm. The application of ULSI, however, is at present largely confined in the area of memory designs, and as such, its impact on traditional, microprocessor-based system design is modest. If advancement in this direction is merely a natural extrapolation from the previous integration generations, then the rise of ASIC (Application-Specific Integrated Circuit) is an unequivocal signal that a directional change in the discipline of system design is in effect. In contrast to ULSI, ASIC employs only well proven technology, and hence is usually at least one generation behind the most advanced processing technology. In spite of this apparent disadvantage, ASIC has become the mainstream of VLSI design and the technology base of numerous entrepreneurial opportunities ranging from PC clones to supercomputers. Unlike ULSI whose complexity can be hidden inside a memory chip or a standard component and thus can be accommodated by traditional system design methods, ASIC requires system designers to master a much larger body of knowledge spanning from processing technology and circuit techniques to architecture principles and algorithm characteristics. Integrating knowledge in these various areas has become the precondition for integrating devices and functions into an ASIC chip in a market-oriented environment. But knowledge is of two kinds.
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Product details

  • Hardback | 232 pages
  • 165.6 x 240.8 x 20.3mm | 521.64g
  • Dordrecht, Netherlands
  • English
  • 1989 ed.
  • 20 Illustrations, black and white; 232 p. 20 illus.
  • 0792390326
  • 9780792390329

Table of contents

1. Introduction.- 1.1 Problem Statement.- 1.2 Approach.- 1.3 Organization of this Book.- 2. Background.- 2.1 The ASIC Challenge.- 2.1.1 ASIC Design Styles.- 2.1.2 The Cutting Edge.- 2.1.3 Impact of ASIC on System Design.- 2.2 Computer Architecture Design for Robotic Control.- 2.2.1 Trends in Architecture Design for Robotics.- 2.2.2 Dedicated Hardware Implementation Considerations.- 2.2.2.1 The Robotic Computation Hierarchy.- 2.2.2.2 The Computational Needs.- 2.2.2.3 Economic Considerations.- 2.2.3 A Survey of Previous Work.- 2.2.3.1 Design Features.- 2.2.3.2 Design Approaches.- 2.2.4 Matching Architecture Styles to Algorithm Characteristics.- 2.2.4.1 Metrics for Evaluating Architectural Effectiveness.- 2.2.4.2 Assessment of Advanced Architecture Concepts.- 2.2.4.2.1 Pipelining.- 2.2.4.2.2 RISC.- 2.2.4.2.3 Systolic Array.- 2.2.4.2.4 Multiprocessors.- 2.3 Robotic Kinematics.- 2.3.1 The Direct Kinematic Solution.- 2.32 The Inverse Kinematic Solution.- 2.3.2.1 Numerical Method.- 2.3.2.2 Closed Form Solution.- 2.3.3 Previous Designs Dedicated to Kinematics Computations.- 2.4 Summary.- 3. A Conceptual Framework for ASIC Design.- 3.1 The Nature of ASIC Design.- 3.1.1 A Comparison of ASIC Design and SIC Design.- 3.1.2 A Decision-Making Perspective versus a Transformation Perspective.- 3.2 The ASIC Design Process.- 3.2.1 VLSI Design Hierarchy.- 3.2.2 VLSI Design Methodology.- 3.2.3 DOEMA: A Model for Methodology Implementation.- 3.2.3.1 The Design Object.- 3.2.3.2 The Design Engine.- 3.2.3.3 The System Manager.- 3.2.3.4 The Expert Assistant.- 3.3 The ASIC Design Hyperspace.- 3.3.1 The Design Space Concept.- 3.3.2 The Architecture Space.- 3.3.3 The Algorithm Space.- 3.4 The ASIC Design Repertoire.- 3.4.1 Resource Configuration.- 3.4.2 Algorithm Restructuring.- 3.4.3 System Partitioning.- 3.5 Summary.- 4. The IKS Chip Design Paradigm.- 4.1 Introduction.- 4.1.1 Assumptions and Constraints.- 4.1.2 Design Philosophy and Objective.- 4.2 An ASIC Architecture Design Methodology.- 4.2.1 Overview.- 4.2.2 Phase 1: Functional Unit Configuration.- 4.2.2.1 Decision Focus: The Functional Unit Profile.- 4.2.2.2 Alternatives and Guidelines.- 4.2.3 Phase 2: Communication Configuration.- 4.2.3.1 Decision Focus: The Dataflow Table.- 4.2.3.2 Alternatives and Guidelines.- 4.2.4 Phase 3: Control Configuration.- 4.2.4.1 Decision Focus: The Control Signal Pattern Profile.- 4.2.4.2 Alternatives and Guidelines.- 4.3 The IKS Chip Architecture Design.- 4.3.1 Design Decisions on Functional Units.- 4.3.1.1 The Characteristics of the IKS Algorithm.- 4.3.1.2 Basic Architectural and Algorithmic Alternatives.- 4.3.1.3 Simulation Results of Fixed-Point Calculation.- 4.3.1.4 MACC Functional Unit Profile.- 4.3.1.5 The IKS Pseudocode.- 4.3.2 Design Decisions on Communication Facilities.- 4.3.2.1 Editing the Dataflow Table.- 4.3.2.2 Timing Model of System Events.- 4.3.2.2.1 Timing of Phase-One Events.- 4.3.2.2.2 Timing of Phase-Two Events.- 4.3.2.2.3 Timing of Cordic Execution.- 4.3.2.2.4 Timing of the Multiplier.- 4.3.2.2.5 Timing Constraints.- 4.3.2.3 The Interconnection Scheme of the IKS Chip.- 4.3.3 Design Decisions on the Control Structure and Mechanisms.- 4.3.3.1 The IKS Chip Symbolic Control Signal Pattern Profile.- 4.3.3.2 Coding Scheme Alternatives.- 4.3.3.3 The MACC Microcode and Instruction Set.- 4.3.3.4 The MACC Microprogram for the IKS Computation.- 4.3.4 Evaluation.- 4.3.4.1 Area.- 4.3.4.2 Performance.- 4.3.4.3 Resource Utilization.- 4.3.4.4 Testability Considerations.- 4.4 Summary.- 5. VHDL Simulation of the IKS Chip.- 5.1 Introduction.- 5.2 VHDL Fundamentals.- 5.2.1 Signal and Associated Concepts for Modeling Behavior.- 5.2.2 Design Entity and Associated Concepts for Describing Structures.- 5.2.3 The VHDL Environment.- 5.3 Simulation Objective and Modeling Approach.- 5.3.1 Data Types.- 5.3.2 Delay Time.- 5.3.2.1 A General Delay Time Model.- 5.3.2.2 Parameter Values.- 5.3.2.3 Programming Strategy.- 5.4 VHDL Description of the IKS Chip.- 5.4.1 Overview.- 5.4.2 The Macros Library.- 5.4.2.1 Latches.- 5.4.2.2 Controlled Input Buffer.- 5.4.2.3 Output Buffer.- 5.4.2.4 Multiplexer.- 5.4.2.5 Counter.- 5.4.2.6 Shifter.- 5.4.2.7 Transmission Gate.- 5.4.3 The Level_2 Library.- 5.4.3.1 The Multiplier Module.- 5.4.3.2 The Z_Adder Module.- 5.4.3.3 The XY_Adders Module.- 5.4.3.4 The Set_Flag Module.- 5.4.3.5 The ROM Module.- 5.4.3.6 The J Register Module.- 5.4.3.7 The R Register Module.- 5.4.3.8 The Cordic Control Module.- 5.4.3.9 The Main Control Module.- 5.4.4 The Level_1 Library.- 5.4.5 The Root Library.- 5.5 Simulation Results.- 5.5.1 Simulation of the Cordic Operation.- 5.5.2 Simulation of MACC Instruction Set.- 5.5.3 Simulation of the IKS Computation.- 5.6 Summary.- 6. Conclusion.- 6.1 Summary.- 6.2 Implications and Future Research.- Appendices.- Appendix A. The Closed Form IKS Algorithm for the PUMA.- Appendix B. The IKS Algorithm in Pseudocodes.- Appendix C. Control Signal Definition.- Appendix D. The MACC Encoding Scheme and Code-Maps.- Appendix E. The MACC Microcode for Computing the IKS.
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